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Application Information
Negative V S Transient
The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations. The biggest diffi-
culty with this circuit is the negative voltage present at
the emitter of the high-side switching device when high-
side switch is turned-off in half-bridge application.
If the high-side switch, Q1, turns-off while the load cur-
rent is flowing to an inductive load, a current commuta-
tion occurs from high-side switch, Q1, to the diode, D2,
in parallel with the low-side switch of the same inverter
leg. Then the negative voltage present at the emitter of
the high-side switching device, just before the freewheel-
ing diode, D2, starts clamping, causes load current to
suddenly flow to the low-side freewheeling diode, D2, as
shown in Figure 34.
DC+ Bus
Figure 36 and Figure 37 show the commutation of the
load current between high-side switch, Q1, and low-side
freewheelling diode, D3, in same inverter leg. The para-
sitic inductances in the inverter circuit from the die wire
bonding to the PCB tracks are jumped together in L C and
L E for each IGBT. When the high-side switch, Q1, and
low-side switch, Q4, are turned on, the V S1 node is
below DC+ voltage by the voltage drops associated with
the power switch and the parasitic inductances of the cir-
cuit due to load current is flows from Q1 and Q4, as
shown in Figure 36. When the high-side switch, Q1, is
turned off and Q4, remained turned on, the load current
to flows the low-side freewheeling diode, D3, due to the
inductive load connected to VS1 as shown in Figure 37.
The current flows from ground (which is connected to the
COM pin of the gate driver) to the load and the negative
Q1
D1
i LOAD
i freewheeling
voltage present at the emitter of the high-side switching
device.
In this case, the COM pin of the gate driver is at a higher
potential than the V S pin due to the voltage drops associ-
V S
Load
ated with freewheeling diode, D3, and parasitic ele-
ments, L C3 and L E3 .
DC+ Bus
Q2
D2
L C1
V LC1
L C2
Q1
D1
i LOAD
D2
Q2
L E1
V LE1
i freewheeling
L E2
Figure 34. Half-Bridge Application Circuits
This negative voltage can be trouble for the gate driver ’s
V S1
L C3
Load
V LC4
V S2
L C4
output stage, there is the possibility to develop an over-
voltage condition of the bootstrap capacitor, input signal
missing and latch-up problems because it directly affects
Q3
D3
D4
Q4
the source V S pin of the gate driver, as shown in Figure
L E3
V LE4
L E4
35. This undershoot voltage is called “negative V S tran-
sient”.
Figure 36. Q1 and Q4 Turn-On
Q1
DC+ Bus
GND
L C1
Q1
D1
i LOAD
D2
L C2
Q2
V S
L E1
V S1
i freewheeling
Load
L E2
V S2
GND
L C3
V LC3
V LC4
L C4
Q3
Q4
Freewheeling
D3
D4
L E3
V LE3
V LE4
L E4
Figure 35. V S Waveforms During Q1 Turn-Off
Figure 37. Q1 Turn-Off and D3 Conducting
? 2009 Fairchild Semiconductor Corporation
FAN7392 Rev. 1.0.4
14
www.fairchildsemi.com
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